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CVE-2020-0574
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable…
Medium5.9EPSS 0.36%
- Published
- Updated
- Reserved
- Assigned by
- intel
Description
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
Scores
| Scored by | CVSS | Score | Vector |
|---|---|---|---|
| NVDNVD · Modified | 3.1 | Medium5.9 | CVSS:3.1/AV:P/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:N |
- EPSS (exploitation in 30 days)
- 0.36% · top 70% of all CVEs (6 Nov 2026)
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The list uses the assigner's score when there is one, then CISA's, then NVD's: Medium 5.9.
Weakness
- Information Disclosure
Affected products
Intel · Intel(R) MAX(R) 10 FPGA
- affected All versions
- affected See advisory https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html
References (1)
- https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html (opens in a new tab)x_refsource_CONFIRMx_transferred
Sources
The same CVE in the primary databases and aggregators, to check against.
- CVE.org record (opens in a new tab)
- CVE List JSON (GitHub) (opens in a new tab)
- NVD (opens in a new tab)
- FIRST EPSS (opens in a new tab)
- OSV.dev (opens in a new tab)
- GitHub Advisories (opens in a new tab)
- CIRCL Vulnerability-Lookup (opens in a new tab)
Badge for a README or a ticket
[](https://trackcve.app/cve/CVE-2020-0574)Record last updated .