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CVE-2020-24512

Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via…

Low3.3EPSS 0.38%
Published
Updated
Reserved
Assigned by
intel

Description

Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

Timeline

  1. ID reserved

    By intel

  2. · 10 months later

    Published

  3. · 5 years later

    Record updated

Changes after publication (a new score, a public exploit, EPSS crossing 1, 10 or 50 %, leaving KEV) are kept since November 2026; earlier ones are not known.

Scores

CVSS scores of CVE-2020-24512, by who scored it
Scored byCVSSScoreVector
NVDNVD · Modified3.1Low3.3CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:L/I:N/A:N
EPSS (exploitation in 30 days)
0.38% · top 67% of all CVEs (7 Nov 2026)
CISA SSVC
Exploitation: none · Automatable: no · Technical impact: partial
Loading the EPSS history…

The list uses the assigner's score when there is one, then CISA's, then NVD's: Low 3.3.

Weakness

Affected products

  • Intel(R) Processors

    • affected See references

References (5)

Sources

The same CVE in the primary databases and aggregators, to check against.

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Record last updated .