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CVE-2026-23554

Use after free of paging structures in EPT

High7.8EPSS 0.13%
Published
Updated
Reserved
Assigned by
XEN

Description

The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.

Scores

CVSS scores of CVE-2026-23554, by who scored it
Scored byCVSSScoreVector
CISA-ADPADP (enrichment)3.1High7.8CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H
NVDNVD · Analyzed3.1High7.8CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H
EPSS (exploitation in 30 days)
0.13% · top 97% of all CVEs (4 Nov 2026)
CISA SSVC
Exploitation: none · Automatable: no · Technical impact: total
Loading the EPSS history…

The list uses the assigner's score when there is one, then CISA's, then NVD's: High 7.8.

Weakness

Affected products

  • Xen · Xen

    • unknown consult Xen advisory XSA-480

What to do

Workaround: There are no mitigations.

References (3)

Sources

The same CVE in the primary databases and aggregators, to check against.

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Record last updated .